In the rapid development of computers many advancements have been seen in the areas of processor speed, throughput, communications, and fault tolerance. Microprocessor speed is measured in cycles per second or hertz. Today's high-end 32-bit microprocessors operate at over 1 GHz (gigahertz), one billion cycles per second, and in the near future this is expected to go substantially higher. At this sort of cycle speed, a clock would have to generate a pulse or cycle at least once each billionth of a second, and usually several orders of magnitude faster. A clock cycle is composed of a high phase and a low phase. A clock duty cycle should be half or 50% of the entire clock cycle, which would indicate that the high phase has the same time duration as the low phase. It is during this clock duty cycle that the processor executes programmed functions.
In order to achieve such a fast timing requirement, quartz crystals are utilized and have been found to be very accurate. However, in order to generate a clock duty cycle, more than the mere presence of a crystal is needed. Additional buffers and electrical circuitry are necessary in order to generate a clock duty cycle. These additional buffers and electrical circuitry, as well as the crystal itself, will generate inaccuracies in the time duration of a given clock duty cycle when the duration of a clock cycle is a billionth of a second or less. Therefore, it is possible for a clock embedded in a microprocessor to generate clock duty cycles that vary slightly in time duration from one clock duty cycle to the next.
Until recently, this very slight difference in the duration of a clock duty cycle has not proven to be a significant problem for microprocessor manufacturers. Processor speeds were slow enough so that these slight differences in the duration of a clock duty cycle were never noticed. However, at cycle speeds of 1 gigahertz and above, even the slightest variation in clock duty cycle duration, otherwise known as clock duty cycle skew, can have a very detrimental impact on processor performance.
The reason for such an impact is that a processor is required to perform a certain operation or execute an instruction or a portion of an instruction within a single clock duty cycle. If a clock duty cycle is shorter than expected, then the processor will not be able to complete the operation or instruction within that clock duty cycle as expected. Further, if a clock duty cycle is longer than desired, then the processor will sit idle for some portion of that clock duty cycle. If a pipeline architecture is employed in a processor, then the presence of clock duty cycle skew would have a further detrimental impact on processor performance. In a pipelined processor architecture, within each clock duty cycle, different instructions or functions are executed at various stages simultaneously. This sort of architecture relies on each instruction or function being executed within a given clock duty cycle. Therefore, failure to complete a function in a given clock duty cycle will defeat the benefits achieved from pipelining.
Another factor that further complicates the manufacturing of high-speed microprocessors is the fact that clock duty cycle skew is not a function of processor design, but rather of the manufacturing process itself and the materials used. No two crystals are alike, and neither are the buffers and additional electrical circuitry required. Therefore, in spite of the very close tolerances in microprocessor manufacture, each microprocessor exhibits a slightly different clock duty cycle skew. Thus, it has not been possible to design a simple circuit that can correct clock duty cycle skew for all microprocessors, since each individual microprocessor may exhibit a different clock duty cycle skew.
Attempts to correct for clock duty cycle skew in high-performance microprocessors have utilized analog integrator circuits that convert the duty cycle time into a voltage value. However, these attempts have proven to be complex to implement and have failed to provide a deterministic system and method for de-skewing clock duty cycles.
Therefore, what is needed is a device and method that will detect clock duty cycle skew within a microprocessor, determine the precise nature of the clock duty cycle skew, and adjust the clock signal to eliminate the clock duty cycle skew. This device and method should further be able to identify different types of clock duty cycle skew and adjust a clock signal accordingly. This device and method should also require as little logic as possible and therefore take up a minimal amount of space within the microprocessor.